3. Senior Design Engineer

Sl.No.

Placement

Description

1

Position

Dependent upon their experience designation will be give

 2

Job Description 

  Atleast 8 years of relevant experience in the semiconductors industry (DfT, IC design and Verification).

  Experience in Analog DfT is a plus.

  Be fluent with all common concepts of DfT and DfT tools.

  Bring in some unique expertise

 

 

 

3

Educational Qualification

B.E or M.Tech in Electronics, Electrical, VLSI

4

Skills & Knowledge 

  Strong knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC level for mixed signal designs.

   Experience in using Mentor DfT tools, Cadence RC and simulator toolsexperience is a plus.

  Define DfT Strategy and Requirement Specification for the design.

  DfT verification for gate-level and timing simulations.

  Work cross sites with design team to define and implement DfT.

  Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.

  Work with STA engineer to define timing constraints for DfT modes.

  Support Test engineer in silicon debug and pattern delivery for ATE.

  Experienced in handling analog DfT simulations.

  Experience in RTL coding, shell scripting.

  Experience in  using version control tools like SVN.