Logo   | Search
About
Project Feasibility Study
Hardware Design &
Fabrication
Program Development & Debugging
Product Characterization & Correlation


 
   
 
 
Enter
 
 
Industry collaboration is tackling IC yield issues
 

Today, companies in the semiconductor ecosystem, from design through manufacturing and test, are doing something the industry as a whole hasn't done before: They are collaborating. The interdependencies among all aspects of the chip development process mean that greater integration, and therefore greater collaboration, is required. One area that has been leading the way for some time has been the connection between design and test. The latest designs, however, require solutions beyond traditional design-for-test (DFT) tools to achieve yield.

To address this need, a successful collaboration has been forged to address the emerging challenges in meeting yield targets at 65 nanometer and beyond. The STDF (Standard Test Data Format) Fail Data Standardization Group, comprising representatives from EDA, ATE, yield management suppliers and leading manufacturers, has been working for more than a year to develop a much-needed data standard that will make it possible to apply fail-data analysis information to the design process to improve time-to-yield.

Manufacturing yield will always be a critical factor for the semiconductor industry. At 65 nm and beyond, the task of collecting and analyzing structural-fail information in volume production is imperative for yield improvements.

Manufacturers increasingly are adopting a volume diagnostics flow in which fail data on internal nodes is collected during volume manufacturing and is processed by the diagnostic tools from the EDA vendors to identify the failing structures. The information on the failing structures is statistically analyzed to identify the yield improvement opportunities.

Although effective structural test techniques exist to collect the necessary data during manufacturing test, to date there has not been an efficient standard format for storing and exchanging the structural-fail data between test and design-for- yield analysis.

The lack of a standard data storage format is further complicated because the typical semiconductor manufacturer uses design tools and test hardware from multiple vendors. To accomplish the necessary integration between test and design to get an efficient yield improvement flow, a standard format is needed for the fail information from the automated test equipment that can then be read by all the EDA tools.

The STDF Fail Data Standardization Group was initiated at the International Test Conference in 2006 to collaborate to define a standard for storing such structural-failure information. The group collectively recognized the importance of this issue. I'm proud to say that we've tackled it in a seamless fashion, and our work has been marked by a shared focus and urgency to establish a working standard as quickly as possible. The initial data model for the standard is ready, and version 1.0 will be released soon.

 
Copyright © ChipTest, All Rights Reserved | Disclaimer
Designed & Developed by Cherry
Home