The 2007 edition of the International Technology Roadmap for Semiconductors (ITRS) projects the technology targets needed to continue to produce semiconductor devices cost-effectively through the year 2022. A significant new focus is the emphasis on More than Moore, the integration of various types of devices, as is deemed cost-effective, either on the same chip or in the same package. “This is ‘heterogenous integration,’ or really consideration of the end application and combining different types of devices in a holistic way to provide functional diversification, as well as the scaling advances we’re used to, in a cost-effective manner,” explained Alan Allan, member of the International Roadmap Committee (IRC) and staff engineer of Intel’s External Programs. Allan provided the keynote address for Semiconductor International's webcast of the 2007 ITRS on Tuesday. Importantly, in the discussion of device technology solutions such as high-k/metal gates or strained silicon, Allan said, “There is a need for parallel paths. No longer can we depend on a single path for the solution, but many solutions will be needed to provide enhancement and management of power as well as productivity solutions.”
During the Q&A portion of the webcast, Allan was joined by key international technology working group (TWG) chairs, including Peter Zeitzoff of the PIDS (Process Integration, Devices and Structures) TWG; Mani Janakiram of Factory Integration; Juan-Antonio Carballo of System Drivers and Design; Chris Case of Interconnect; Will Conley and Steve Mackay of Lithography; and Jim Jewett and Walter Worth of ESH.
Regarding node definition, the 2007 ITRS continues with last year’s position that they would like to eliminate references to the term “technology node,” because today there is no single indicator of feature scaling. For years, DRAM set the pace in terms of scaling because DRAM had the tightest contacted metal half-pitch, therefore it was the metric used for technology node. In recent years, flash memory has replaced DRAM as the technology leader with its more aggressive uncontacted poly half-pitch. Therefore, reference to a particular device type (MPU, DRAM, flash) is necessary, as each follows its own roadmap.
Lithography — what works for 32 nm?
There was great interest from the audience on what will be the manufacturable, cost-effective lithography solution for 32 nm high-volume production. “If we talk about 32 nm node, meaning the 32 nm half-pitch, all companies are performing device development using double patterning right now,” Conley stated. “Among many approaches, the spacer approach is the furthest along by far; and most companies are banking on EUV being ready for the 22 nm half-pitch.” When asked if regular design rules would stimulate the use of a spacer pitch division approach in non-flash devices, Conley said, “We want to find the cheapest solution, both from a materials standpoint and from a cycle-time cost perspective. If we have an all-track approach, that’s probably the one we would like to take.” His colleague, Steve Mackay, added that “it’s not just about regular patterns, but also the poly, metal and other layers and how they all fit together. You have to look at transistor and cell designs. You can’t just have regular grid patterns and then it all takes off.”
In the area of nanoimprint lithography, Conley did not look favorably on the technology for mainstream semiconductor applications, but pointed out that it held promise for related industries such as micromachining. “The major complaint is that it’s a 1X technology, and for those of us with X-ray experience, we know the problems — the concerns of overlay and throughput. But companies are considering it for early device learning.”
Interconnects/3-D areas hot
When asked if the low-k delay would continue, Case remarked, “We love questions about low-k, and also the fact that we’ve never gotten the low-k roadmap right; but if I were to forecast whether a k effective (keff) of 2.0 was going to be achieved with a materials-based delivery, I would say it probably will not happen. That doesn’t mean it won’t be achieved with an air-gap approach, a partial air-gap approach, which is probably a more viable solution due to the integration challenges the industry has run into with porous materials.” Case points to the red brick wall in the low-k roadmap, where no known solutions exist below keff<2.4.
Nevertheless, shorter delay times can be achieved by other means, such as 3-D stacking approaches. Case contends that, technically, many of the challenges with through-silicon vias (TSVs) and the various manufacturing steps needed to make stacked chips a reality have largely been solved. “Companies have demonstrated 100:1 aspect-ratio holes. The real challenge is achieving satisfactory cost when implementing a relatively new approach to the package.” Between the Interconnect TWG and Assembly and Packaging TWG, several 3-D approaches have been evaluated and put forth as potential solutions in the ITRS.
When asked whether 3-D stacking will primarily fall to the fab or the assembly and packaging house, Case said he thinks both will happen. “The natural extension is for traditional factories to extend their toolsets for the high-density approaches, while you’ll see low-density approaches from the packaging side.”
Efficient factories
The Factory Integration TWG has a strong focus on improving the efficiency of tools in terms of capability, reliability and availability. “There are built-in losses, from how the equipment is pumped down to start-up procedures and how preventive maintenance is performed. We are looking at sleep modes for energy conservation and a metric to address how energy is consumed,” Janakiram said. While he concedes that there will always be equipment specialization, the group is proposing aggressive steps to improve the productivity of 300 mm factories to cut costs and improve efficiencies.
