San Francisco (CA) – This year’s IEEE International Solid State Circuits Conference (ISSCC) will offer once again hundreds of briefing sessions on the latest developments in the semiconductor industry. Among the most interesting in the microprocessor category are sessions about a 45 nm Cell processor, Intel’s quad-core Itanium Tukwila and entry-level Silverthorne CPUs as well as Sun’s 16-core Niagara 3 chip

Information provided through the ISSCC 2008 program are brief, but the document - which was posted earlier this month on the ISSCC website – offers some insight what we can expect to learn this year. Sony is apparently working on a 65 nm to 45 nm migration of its Cell Broadband Engine. Sony claims that the chip area size will be reduced by 34% and the 45 nm Cell will consume 40% less power than the 65 nm generation. The company also works on improving the design for manufacturability (DFM) for Cell to simplify the CPU production process.

Intel remains one of the major contributors to the conference and has submitted a total of 16 papers. We hear that there will be an update on the company’s Terascale effort, even if there is no dedicated session mentioned in the ISSCC program. Instead, it appears that Intel will have two major focus areas: The upcoming Tukwila Itanium processor and Silverthorne, which will be heading towards entry-level systems as well as Mobile Internet Devices (MIDs).

The ISSCC document describes Tukwila as a two-billion transistor 65 nm quad-core processor with a die size of 699 mm2. The CPU integrates 30 MB of L2 cache and 96 GB/s processor-to-processor bandwidth through the firm’s new “QuickPath” Interconnect. The peak memory bandwidth of Tukwila is 34 GB/s. Intel says Tukwila has three times the circuitry of the current Itanium generation with Montvale core.  

Substantially smaller will be the Silverthorne processor: Intel says the 45 nm CPU will house 47 million transistors on a 25 mm2 area. The x86 CPU which is scheduled for a launch later this year will have a 2-issue, in-order pipeline with 32KB iL1 and 24KB dL1 caches, a 512 KB L2 cache, integer and floating point execution units, and support FSB533. Silverthorne will be manufactured in a 441-ball μFCBGA package.

Another Intel session will focus on test results with phase change memory, a potential successor for flash memory. The company will discuss a 90 nm 256 MB multi-level cell chip, which apparently has been put through 100,000 erase and write cycles.

Sun has also a few interesting briefings lined up and apparently is ready to talk about its third-generation Niagara processor: The outlined 65 nm Niagara 3 has 16 cores, runs at 2.3 GHz, processes 32 threads and has a die size of 396 mm2.