The Semiconductor Research Corporation (SRC), through its Global Research Collaboration program, announced a collaborative effort between the Indian Institute of Technology at Bombay (IIT) and Applied Materials, Inc. to advance NAND flash memory technology. NAND flash is one of the most rapidly evolving technologies today, enabling a large variety of portable electronic devices from media players to navigation systems to solid-state drives for laptop computers. This international research effort is focused on providing breakthrough technology that can lead to a broad range of significantly smaller and more powerful portable electronic devices in the next five years.
"IIT is deeply engaged in NAND flash memory research and has been an excellent partner in helping us to continue to drive solid-state memory technology development," said David Kyser, senior director of strategic external research in Applied Materials' department of Advanced Technology/CTO. "This type of collaboration, facilitated by SRC, is an efficient way to drive the commercialization of new technologies: Industry provides near-term focus while academia brings innovation and scientific rigor."
An example of this important research has recently been presented by IIT and Applied Materials at the recent International Reliability Physics Symposium in Phoenix, AZ. As NAND flash devices continue to scale, problems with reliability and lifetime caused by cell-to-cell interference arise when conventional floating-gate (FG) memory cells are used. Charge-trap flash (CTF) is a promising replacement for FG because it exhibits negligible cell-cell interference, yet has a similar structure and manufacturing process to FG and is thus attractive for memory device manufacturers to implement using existing equipment.
The primary innovation is the development and optimization of an engineered trap layer consisting of two nitride layers with different compositions, reinforced by a silicon oxy-nitride barrier layer. This novel structure was found to exhibit negligible cycling degradation and optimum programming characteristics, offering an alternative to approaches using more complex high-k and metal gate materials. The new structure has the potential to scale down to the sub-3xnm technology node, offering much higher storage densities than are available today.
"Materials development and process integration are the keys to implementation of the new cell designs," said Souvik Mahapatra, associate professor in the department of electrical engineering at IIT-Bombay. "The diverse, but complementary, perspectives among this team of researchers have served to more quickly uncover the physical mechanisms of endurance damage. These have provided for better understanding of reliability and consequently improved device design."
"This collaboration reflects SRC's commitment to tapping the deep talent offered by Indian research and the potential for significant progress in memory design," said Steven Hillenius, executive vice president of SRC. "The success from this work should lead to higher standards for functionality in future electronics."
